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Semiconductor Engineering
semiengineering.com > the-on-device-llm-revolution

The On-Device LLM Revolution

2+ hour, 26+ min ago  (1044+ words) Why 3B to 30B models are moving to the edge " and what that means for silicon. This isn't a passing trend. It's an architectural inflection point driven by latency requirements, privacy mandates, cost pressures, and user experience demands that cloud inference simply…...

Semiconductor Engineering
semiengineering.com > force-fields-will-accelerate-atomistic-simulations-by-10000x-in-2026-unlocking-new-era-of-discovery

Force Fields Will Accelerate Atomistic Simulations By 10,000× In 2026, Unlocking New Era Of Discovery

1+ day, 2+ hour ago  (610+ words) Machine learning enables a transformative leap in the modeling of atomic interactions. By Anders Blom and Igor Markov "Force fields" have long captured our imagination " the invisible shields of science-fiction lore that protect starships and superheroes from harm. But in…...

Semiconductor Engineering
semiengineering.com > blog-review-feb-18-2

Blog Review: Feb. 18

2+ day, 2+ hour ago  (551+ words) Agentic disruption; data center PUE; scaling AI; RTOS; dropping toast. Synopsys" Raja Tabet anticipates deployment of an agentic AI workforce within the next 12 to 24 months that can take on different engineering personas, such as a digital implementation agent, a verification…...

Semiconductor Engineering
semiengineering.com > llm-based-learning-platform-for-chip-design-education-rptu

LLM-Based Learning Platform For Chip Design Education (RPTU)

5+ day, 2+ hour ago  (339+ words) RPTU University of Kaiserslautern-Landau researchers published "From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs." Abstract "This paper presents an LLM-based learning platform for chip design education, aiming to make chip design accessible to beginners…...

Semiconductor Engineering
semiengineering.com > formal-verification-first-how-ai-supports-but-cannot-replace-it

Formal Verification First: How AI Supports But Cannot Replace It

1+ week, 2+ hour ago  (406+ words) In verification, speed without provable correctness is not progress. At a recent VLSI-D panel, industry leaders explored one of the most pressing topics in silicon design today " the intersection of AI-powered EDA, which is revolutionizing chip design for tomorrow. Ashish…...

Semiconductor Engineering
semiengineering.com > scaling-llama-cpp-on-neoverse-n2-solving-cross-numa-performance-issues

Scaling llama.cpp On Neoverse N2: Solving Cross-NUMA Performance Issues

1+ week, 1+ day ago  (563+ words) NUMA-aware optimizations can deliver up to 55% faster text generation. This blog post explains the cross-NUMA memory access issue that occurs when you run llama.cpp in Neoverse. It also introduces a proof-of-concept patch that addresses this issue and can provide…...

Semiconductor Engineering
semiengineering.com > modern-trends-in-floating-point

Modern Trends In Floating-Point

2+ week, 1+ day ago  (290+ words) New applications drive a growing preference for energy efficiency and throughput over strict precision. This is where floating-point arithmetic comes in, a technique that now sits at the heart of modern computing and underpins everything from scientific data to machine…...

Semiconductor Engineering
semiengineering.com > scaling-ultra-low-power-edge-intelligence-for-smart-devices

Scaling Ultra-Low-Power Edge Intelligence For Smart Devices

2+ week, 1+ day ago  (317+ words) Processing temporal sensor data at the source in real time. For decades, the data collection pipeline for sensors has been the exact same'measure, transmit, and process elsewhere. While it's been a failproof method all these years, it's also resulted in…...

Semiconductor Engineering
semiengineering.com > blog-review-feb-4-2

Blog Review: Feb. 4

2+ week, 2+ day ago  (391+ words) Siemens" Tova Levy examines thermal management in 3D-IC, including why heat behaves differently in vertical stacks and how to analyze and manage thermal risk earlier and more predictably to ensure a design can meet performance, reliability, and time-to-market targets. Synopsys…...

Semiconductor Engineering
semiengineering.com > ml-for-energy-performance-aware-scheduling-on-heterogeneous-multicore-architectures-cambridge

ML for Energy-Performance-Aware Scheduling On Heterogeneous Multicore Architectures (Cambridge)

2+ week, 3+ day ago  (132+ words) University of Cambridge researchers published "Machine Learning for Energy-Performance-aware Scheduling." Abstract "In the post-Dennard era, optimizing embedded systems requires navigating complex trade-offs between energy efficiency and latency. Traditional heuristic tuning is often inefficient in such high-dimensional, non-smooth landscapes. In this…...